On chip Static Random Access Memories (SRAMs) are critical component of the modern system-on-a-chip (SOC) solutions. As CMOS technology has scaled into deep nanometric regime, the density of static random access memory (SRAM) has increased manifolds. As a consequence, for the same die area, density of SRAM bit-cells has increased and there is a great motivation to improve reliability, yield and performance of dense SRAM arrays.
A typical SRAM array is organized in multiple rows (N) and columns (M) as shown in FIG. 1. Each bit-cell stores one bit of data; a logic value of one or zero. Each bit-cell in a typical row and column is controlled through a word-line (WL) and a pair of differential bit-lines (BLT and BLC) shown as Bi in FIG. 1. Based upon the state of the SRAM array the plurality of the bit-cells are in read, write or retention mode. Generally, data in SRAMs is organized in words, and at any given time, only one word-line is selected. A row decoder decodes the row address and the driver activates a row through WL signal. Concurrently, a column decoder takes the column address information to decode the column address and activate the column. The number of columns activated depends upon the word size. In a write operation, column decoder and bitline drivers would set the bit-lines to appropriate values (logic one or zero) based upon the input data (Di). During a read operation, sense amplifiers takes differential input from the selected bit-cell to produce a full logic swing output (Qi) and to determine the value of the stored data bit. Column multiplexer is used to selectively connect a number of columns to a sense amplifier. It is achieved by multiplexing the bit-lines in the columns to a single sense amplifier.
In SRAMs, voltage sense amplifier and/or current sense amplifiers are typically used to sense data in the selected cell and amplify it to full swing. Usage of sense amplifier results in substantial area, power and energy savings. Current mode sense amplifiers are preferred when faster speed of operation is required. A current mode sense amplifier senses and amplifies the current from the selected cell. Alternatively, a voltage mode sense amplifier senses the differential voltage across the selected bitlines and amplifies it. A voltage mode sense amplifier is generally preferred for low-power applications.
All amplifiers including sense amplifiers have a finite, intrinsic offset voltage. Inherent manufacturing process variation, transistor mismatch, temperature, etc. contribute to the offset voltage of a sense amplifier. Therefore, for robust decision making, differential input must be larger than the worst case offset voltage of the sense amplifier.
FIG. 2(a) illustrates a circuit diagram of a conventional current mode sense amplifier. FIG. 2(b) shows the waveforms which illustrate its timing operation. In this sense amplifier the bitlines are connected to the gates of two NMOS transistors MN1, MN2. A Sense Amplifier Enable (SAE) signal which is initially kept low keeps MP1 and MP2 on and MN5 off. This causes the output nodes OPT and OPC, to pre-charge to logic high level. The sensing operation begins when YMUX signal transitions from high to low. This connects bitlines BLC, BLT to the sense amplifier through the gating transistors MP5, MP6 to the gate of sensing transistors, MN1, and MN2, respectively. Subsequently, the SAE signal is activated to logic high which switches off MP1 and MP2 and turn on MN5. In this process, the sense amplifier is powered on. At this time, the differential voltage at bitlines connected to the gates of MN1 and MN2 cause an imbalanced current to flow in the cross-coupled inverter-pair comprising of MN3, MP3 and MN4, MP4. This imbalance causes different discharging speeds at OPT and OPC from the precharged voltage. Since OPT, OPC are pre-charged to VDD, thus, both PMOS transistors MP3, MP4 are off until the corresponding gate voltage, i.e., output voltage reaches (VDD−VthP). Now, the positive feedback amplifies the output voltage difference and fully turns on one NMOS and one PMOS transistor of each cross-coupled inverter pair. For example, if the MN3 is fully turned on which leads to node OPT discharged to ground, MP4 will turn on. As a result, outputs OPT and OPC achieved complementary logic values.
FIG. 3, illustrates a latch-type sense amplifier which is similar to an SRAM cell with two back-to-back inverters forming a latch. Two access transistors, MP5 and MP6 couple the latch nodes, OPT and OPC, to the BLT and BLC, respectively. Sense Amplifier Enable (SAE) signal which is initially kept low keeps MP1 and MP2 on and MN3 off. This causes the output nodes OPT and OPC, to pre-charge to logic high level. The sensing operation begins when YMUX signal transitions from high to low. This connects bitlines BLC, BLT to the sense amplifier through the gating transistors MP6, MP5 to the gate of sensing transistors, MN1, and MN2, respectively. Subsequently, the SAE signal is activated to logic high which switches off MP1 and MP2 and turn on MN3. In this process, the sense amplifier is powered on. At this time, the differential voltage at bitlines connected to OPC and OPT creates an imbalance between overdrive voltage (VGS−VT) of latching transistors that leads to regenerative feedback and signal amplification.
One of the problems with the sense amplifier illustrated in FIG. 3 is the threshold voltage mismatch between sensing transistors MN1 and MN2. The differential input signal must be greater than the threshold voltage mismatch, and the associated offset voltage, for the sense amplifier to make a reliable decision. FIG. 4, depicts a threshold mismatch mitigation sense amplifier for memories. The operation of this circuit is described in greater detail by Gupta et. al. in U.S. Pat. No. 7,227,798 B2. Compared to the sense amplifier illustrated in FIG. 3, access transistors, MP4 and MP3 connect bitlines, BLT and BLC, to the latching nodes (OPT, and OPC) of the sense amplifier. Transistor pairs MN1 and MN3; and MN2 and MN4, are in series with their respective gates connected to the bit-lines, BLT and BLC. Putting it alternatively, this arrangement is similar to the cascode amplifier with some important differences, and advantages. Firstly, both transistors in the proposed cascode (e.g., MN1 and MN3; or MN2 and MN4) are sensing transistors with bit-line or its complement signal at their respective gates. As a result, two pairs of sensing transistors work in tandem to amplify the signal.
Secondly, such an arrangement has a capability of compensating threshold voltage mismatch of sensing pair transistors MN3 and MN4 and storing the mismatch on their respective source nodes (nodeA and nodeB) which can be explained with the timing of the sense amplifier illustrated in FIG. 4(b). The read operation starts with bit-lines, BLT and BLC, pre-charged to VDD. Subsequently, a decoded Wordline, WL, makes a positive transition connecting an SRAM bit-cell to BLT and BLC. Assuming without the loss of generality, the BLT is discharged to (VDD−ΔV) owing to the charge sharing with the data stored in the bit-cell, while BLC remains at VDD. During this period the SAED is low, therefore node OPT is discharged to (VDD−ΔV) while OPC remains at VDD. Since transistors MN3 and MN4 are cross coupled, nodeA and nodeB are charged to voltages (VDD−VTMN3), and (VDD−VTMN4) before MN3 and MN4 are turned-off, respectively. VTMN3 and VTMN4 are the threshold voltages of MN3 and MN4, and consequently, the potential difference between nodeA and nodeB now stores the threshold voltage mismatch between sensing transistors MN3 and MN4 before sense amplifier starts sensing operation.
The concept of threshold voltage mismatch compensation can be further explained as follows: Assuming that the VTMN3=VTMN4=VTN, after the precharge stage, the voltage at nodeA=the voltage at nodeB=(VDD−VTN). As illustrated in the timing diagram in FIG. 4(b), the SAE signal makes a positive transition enabling the sense amplifier. In addition, the BLT and BLC nodes are still coupled to OPT, gate of MN1; and to OPC, and the gate of MN2, respectively. Further, assuming that the voltage at BLT=(VDD−Δ), and voltage at BLC=VDD when the SAE makes a positive transition. The initial overdrive voltage conditions for MN3 and MN4 at this moment are: (i) [VGSMN3−VTN]=[{(VDD−ΔV)−(VDD−VTN)}−VTN]=[(VTN−ΔV)−VTN]=(−ΔV); and (ii) [VGSMN4−VTN]=[{(VDD)−(VDD−VTN)}−VTN]=[(VTN)−VTN]=0. As it is apparent to a person knowledgeable in the art; at that instance the transistor MN3 is off by the ΔmV, while the transistor MN4 is precisely at the on/off boundary.
Now considering the realistic scenario where threshold voltage of MN3 and MN4 are VTMN3 and VTMN4 owing to the process variation. Following the same argument as describe in the preceding paragraph, the initial overdrive voltage conditions for MN3 and MN4 just before, the transistor MN5 is turned on by the SAE positive transition are: (i) [VGSMN3−VTMN3]=[{(VDD−ΔV)−(VDD−VTMN3)}−VTMN3]=[(VTMN3−Δ)−VTMN3]=(−ΔV); and (ii) [VGSMN4−VTMN4]=[{(VDD)−(VDD−VTMN4)}−VTMN4]=[(VTMN4)−VTMN4]=0. Therefore, the initial overdrive voltages of MN3 and MN4 remain the same in spite of their different threshold voltages. In other words, the threshold mismatch between the MN3 and MN4 sensing transistors is compensated. Subsequently, SAED makes a positive transition uncoupling bitlines from the sense amplifier. Now, the sense amplifier is powered and resolves the differential input to full swing level.
One of the disadvantages of the sense amplifier described in U.S. Pat. No. 7,227,798 B2 is its low-voltage operation. There are four transistors that are in series between the power supply voltage, VDD, and the ground. As a result, the circuit is difficult to make it work at lower power supply voltages. In addition, at lower power supply voltage, the differential input signal voltage at bitlines is likely to be relatively small making the task of the sense amplifier even more difficult.